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HV57009 64-Channel Serial to Parallel Converter with P-Channel Open Drain Controllable Output Current
Features
HVCMOS(R) technology 5.0V CMOS Logic Output voltage up to -85V Output current source control 16MHz equivalent data rate Latched data outputs Foreward and reverse shifting options (DIR pin) Diode to VDD allows efficient power recovery
General Description
The HV570 is a low-voltage serial to high-voltage parallel converter with P-channel open drain outputs. This device has been designed for use as a driver for plasma panels. The device has two parallel 32-bit shift registers, permitting data rates twice the speed of one (they are clocked together). There are also 64 latches and control logic to perform the blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to VSS, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), or the BL (blanking) inputs. Transfer of data from the shift registers to latches occurs when the LE input is high. The data in the latches is stored when LE is low. The HV570 has 64 channels of output constant current sourcing capability. They are adjustable from 0.1 to 2.0mA through one external resistor or a current source.
Functional Block Diagram
DI/O2A DI/O1A LE BL DD
I/O DIR CLK Latch SR1 Latch
HVOUT1 HVOUT2 HVOUT3 * * * HVOUT32 HVOUT33 HVOUT34 HVOUT35 * * * HVOUT64
Latch SR2 Latch I/O DI/O2B DI/O1B Programmable Current VSS VBP +IN -IN
Note: Each SR (shift register) provides 32 outputs. SR1 supplies outputs 1 to 32 and SR2 supplies outputs 33 to 64.
HV57009
Ordering Information
Device HV57009 Package Options 80-Lead PQFP HV57009PG-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter Supply voltage, VDD1 Output voltage , VPP1 Logic input levels1 Ground current2 Continuous total power dissipation3 Operating temperature range Storage temperature range Lead temperature 1.6mm from case for 10 seconds Value -0.5V to +7.5V VDD + 0.5V to -95V -0.3V to VDD + 0.3V 1.5A 1200mW -40C to +85C -65C to +150C 260C
Pin Configuration
80 1
80-Lead PQFP (PG)
(top view)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. Notes: 1. All voltages are referenced to VSS 2. Limited by the total dissipated in the package. 3. For operation above 25C ambiant derate linearly to maximum operating temperature at 20mW/C.
Product Marking
HV57009PG
LLLLLLLLLLL YYWW CCCCCCCCC AAA
L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = "Green" Packaging
80-Lead PQFP (PG)
Recommended Operating Conditions
Symbol VDD HVOUT VIH VIL fCLK TA Parameter Logic supply voltage HV output off voltage High-level input voltage Low-level input voltage Clock frequency per register Operating free-air temperature Min 4.5 -85 VDD - 1.2V 0 DC -40 Max 5.5 VDD 1.2 8.0 4.5 +85 Units V V V V MHz C
Notes: Power-up sequence should be the following: 1. Apply ground 2. Apply VDD 3. Set all inputs (DIN, CLK, LE) to a known state Power-down sequence should be the reverse of the above
2
HV57009
DC Electrical Characteristics (All voltages are referenced to V
Symbol IDD INN IDDQ VOH VOL IIH IIL ICS ICS Parameter VDD supply current High voltage supply current Quiescent VDD supply current High level output Low level output Data Out HVOUT Data Out Min VDD - 0.5V +1.0 High output source current -0.1 HV output source current for IREF = 2.0mA 10 mA %
SS
, VSS = 0, TA = 25OC)
Max 15 -10 100 VDD +0.5 1.0 -1.0 -2.0
Units mA A A V V V A A mA
Conditions VDD = VDD max, fCLK = 8.0MHz Outputs off, HVOUT = -85V (total of all outputs) All inputs = VDD, except +IN = VSS = GND IO = -100A IO = -2.0mA IO = 100A VIH = VDD VIL = 0V VREF = 2.0V, REXT = 1K, see Figures 1a and 1b VREF = 0.1V, REXT = 1K, see Figures 1a and 1b VREF = 2.0V, REXT = 1K
High-level logic input current Low-level logic input current
Note: Current going out of the chip is considered negative.
AC Electrical Characteristics (Logic signal inputs and data inputs have t , t 5ns [10% and 90% points] for measurements)
r f
Symbol fCLK tWL, tWH tSU tH tON, tOFF tDHL tDLH tDLE tWLE tSLE tr, tf
Parameter Clock frequency Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time from latch enable to HVOUT Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high LE pulse width LE set-up time before clock rises Max. allowable clock rise and fall time (10% and 90% points)
Min DC 62 20 15 45 25 0 -
Max 8.0 4.5 500 150 150 100
Units MHz ns ns ns ns ns ns ns ns ns ns
Conditions Per register When cascading devices ------CL = 15pF CL = 15pF CL = 15pF ---------
3
HV57009
Input and Output Equivalent Circuits
VDD VDD
Input
Data Out
VSS Logic Inputs
VSS Logic Data Output
VDD VDD
ICS PCNTRL Input To Internal Circuits
HVOUT VSS Analog Input High Voltage Output
Shift Register Operation
HVOUT32 DIR = VDD; CW (HVOUT1HVOUT64) DIR = VSS; CCW (HVOUT64HVOUT1) HVOUT33
*
*
* SR1 * CW
*
*
* CW SR2 HVOUT2 HVOUT1 Pin 25 26 36 37
*
*
*
HVOUT63 HVOUT64
DIR = VDD DI/O1A DI/O2A DIR = VSS DI/O2A DI/O1A
DI/O2B DI/O1B DI/O1B DI/O2B
4
HV57009
Switching Waveforms
VDD Data Input 50% tSU CLK 50% tWL 50% tWH 50% VSS Data Out tDLH 50% tDHL VDD VSS Data Valid tH 90% 50% 50% VSS tf tr VDD 10% 10% 90% 50% VSS VDD
LE tDLE
50% tWLE
50% tSLE
VDD VSS
HVOUT w/ data input LOW
Previous IO = IREF tOFF
90% 10% IO = 0
VDD HVOUT (off)
HVOUT w/ data input HIGH
10% Previous IO = 0 tON
90%
IO = IREF
VDD HVOUT (off)
Function Table
Inputs Function Data In X L H X DI/O1-2A I/O relation DI/O1-2A DI/O1-2B DI/O1-2B CLK X _ _ _ _ X _ _ _ _ _ _ _ _ LE X H H L H L L H BL L H H H H H H H DIR X X X X H H L L Shift Reg * L.....L H.....H * QnQn+1 QnQn+1 QnQn-1 QnQn-1 Outputs HV Outputs ON ON OFF Inversion of stored data New ON or OFF Previous ON or OFF Previous ON or OFF New ON or OFF Data Out * L H * DI/O1-2B DI/O1-2B DI/O1-2A DI/O1-2A
All O/P high Data falls through (latches transparent) Data stored in latches
Note: * = dependent on previous stage's state. See Figure 7 for DIN and DOUT pin designation for CW and CCW shift. H = VDD (Logic)/VNN (HV Outputs) L = VSS
5
HV57009
Typical Current Programing Circuits
0.1F VDD
0.1F
VDD
HV57009
VBP VBP To other outputs Logic -+ IOUT HVOUT +IN -IN VSS REXT IREF VREF RD*10K CD*390pF
HV57009
To other outputs Logic -+
IOUT HVOUT
+IN
-IN
VSS VREF REXT IREF
RD*10K CD* 390pF
Figure 1a: Negative Control
Figure 1b: Positive Control
*Required if REXT > 10K or REXT is replaced by a constant current source.
Since IOUT = IREF =
VREF REXT
Given IOUT and VREF, the REXT can be calculated by using: REXT = V VREF = REF IOUT IREF
Therefore: If IOUT = 2.0mA and VREF = -5.0V REXT = 2.5K. If IOUT = 1.0mA and REXT = 1.0K VREF = -1.0V. If REXT >10K, add series network RD and CD to ground for stability as shown. This control method behaves linearly as long as the operational amplifier is not saturated. However, it requires a negative power source and needs to provide a current IREF = IOUT for each HV570 chip being controlled. If HVOUT +1.0V, the HVOUT cascode may no longer operate as a perfect current source, and the output current will diminish. This effect depends on the magnitude of the output current.
4
The intersection of a set of IOUT and VREF values can be located in the graph shown below. The value picked for REXT must always be in the shaded area for linear operation. This control method has the advantage that VREF is positive, and draws only leakage current. If REXT > 10K, add series network RD and CD to ground for stability as shown. Note: Lower reference current IREF, results in higher distortion, ICS, on the output.
HV570 IOUT vs. VREF
0.1K
0.2K
0.5K
1K
2K
3K
3
IO U T (mA)
2
5K
1
0
0
1
2
VREF (Volts)
3
4
5
6
HV57009
Pin Function
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function HVOUT24 HVOUT23 HVOUT22 HVOUT21 HVOUT20 HVOUT29 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 HVOUT6 HVOUT5 Pin # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 37 39 40 Function HVOUT4 HVOUT3 HVOUT2 HVOUT1 DIO/1A DI/O2A NC NC LE CLK BL VSS DIR VDD -IN DI/O2B DI/O1B NC +IN VBP Pin # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Function HVOUT64 HVOUT63 HVOUT62 HVOUT61 HVOUT60 HVOUT59 HVOUT58 HVOUT57 HVOUT56 HVOUT55 HVOUT54 HVOUT53 HVOUT52 HVOUT51 HVOUT50 HVOUT49 HVOUT48 HVOUT47 HVOUT46 HVOUT45 Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function HVOUT44 HVOUT43 HVOUT42 HVOUT41 HVOUT40 HVOUT39 HVOUT38 HVOUT37 HVOUT36 HVOUT35 HVOUT34 HVOUT33 HVOUT32 HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25
Note: Pin designation for DIR = VDD. A 0.1F capacitor is needed between VDD and VBP (pin 40) for better output current stability and to prevent transient cross-coupling between outputs. See Fig. 1a and 1b.
7
HV57009
80-Lead PQFP Package Outline (PG)
20x14mm body, 0.80mm pitch
D D1
1 E E1
Note 1 (Index Area D1/4 x E1/4)
L2
80
Gauge Plane
1
e
b
L L1
Seating Plane
Top View View B
A A2 A1
Seating Plane
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 2.80 3.40
A1 0.25 -
A2 2.55 2.80 3.05
b 0.30 0.45
D 23.65 23.90 24.15
D1 19.80 20.00 20.20
E 17.65 17.90 18.15
E1 13.80 14.00 14.20
e 0.80 BSC
L 0.73 0.88 1.03
L1 1.95 REF
L2 0.25 BSC
0O 3.5 7
O O
1 5O 16O
JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995. Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV57009 A040907 8

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